Atomera Incorporated Q2 FY2025 earnings call

• Scott Bibaud discussed semiconductor industry macro factors favoring Atomera's product initiatives, with wafer activity higher than usual. Updates on licensees like STMicro, including delay in BCD 110 process rollout to 300-millimeter but excitement over revenue potential. Progress with customers JDA1, JDA2, fabless licensee, and foundry licensee. Advancements in GaN for power and RF, including collaboration with Incize for RF characterization. Expansion of RF-SOI offerings to include LNA benefits, with new wafer runs using Soitec's ultrathin RF-SOI wafers. Over 400 issued and pending patents, joined National Semiconductor Technology Center. - Franc Laurencio discussed financials, maintaining non-GAAP OpEx guidance for 2025 at $17.25M to $17.75M, tracking to low end. Expecting small NRE revenue in Q3 from certain shipments, milestone payments from STMicro expected next year. Spreading outsourced fabrication work over multiple vendors, making progress in sales/marketing and engineering leadership.

GAAP net loss for Q2 2025 was $5 million or $0.17 per share, compared to a net loss of $4.4 million in Q2 2024 ($0.16 per share). GAAP operating expenses in Q2 2025 were $5.2 million, an increase of $565,000 from Q2 2024. Non-GAAP net loss in Q2 2025 was $4 million vs. $3.6 million in Q2 2024. Cash and cash equivalents as of June 30, 2025, were $22 million, down from $24.1 million on March 31. Used $3.5 million of cash in operating activities during Q2, compared to $4.8 million in Q1.

• Maintaining non-GAAP OpEx guidance for 2025 at $17.25M to $17.75M, tracking to low end. - Expecting small NRE revenue in Q3 from wafer shipments to specific customers. - Milestone payments from STMicro for process qualification not expected until next year.

Q: To what degree is the work done with STMicro on 200-millimeter useful for 300-millimeter?

A: STMicro has learned a lot about depositing MST and analyzing results on 200-millimeter, which will help with 300-millimeter. They have expertise in depositing and integrating MST, and while there are some steps like getting 300-millimeter tools, progress is expected.

Q: Describe the transformative customers' large-scale demos?

A: One customer is doing a very large demo run with many wafers and tests across different splits, allowing quick learning cycles. Another is working on multiple wafer runs in different application areas with support from Atomera.

Q: Does becoming a member of NSTC increase possibility of CHIPS Act subsidies?

A: Yes, as NSTC provides access to testing and metrology needed for advanced transistor structures, and helps in the conversation for funding opportunities under CHIPS Act.