Aehr Test Systems Q2 FY2026 earnings call

Management Statement and Operational Highlights

• Market Focus: Emphasized AI and data center infrastructure as key growth drivers for semiconductor test and burn-in.
• Wafer-level Burn-in Progress: Expanded engagements across AI processors, flash memory, silicon photonics, gallium nitride, and hard disk drives. Lead AI customer developing next-gen processor and discussing additional capacity. Partnership with ISE Labs to accelerate time to market for wafer-level test and burn-in.
• Packaged-part Burn-in Progress: Secured key device wins for Sonoma system, received significant orders, and completed development of next-generation Sonoma system.
• Segment Updates: Silicon photonics lead customer firmed up production ramp; gallium nitride supported lead customer with delays resolved and engaged with new potential customers; silicon carbide demand weighed toward end of fiscal year; hard disk drives installing additional systems with plans for more purchases.

Segment Performance

• Wafer-level burn-in: During the quarter, expanded engagements and completed additional production installations across several end markets. The lead AI wafer-level burn-in customer is developing its next-generation processor and discussing additional capacity. A strategic partnership with ISE Labs was announced to deliver advanced wafer-level test and burn-in services. Developed new fine-pitch WaferPaks for high-current AI processors and had 2 additional AI processor companies planning wafer-level benchmark evaluations. For silicon photonics, the lead customer firmed up production ramp starting early fiscal '27. In gallium nitride, supported lead production customer with delays resolved, and engaged with new potential customers. In silicon carbide, demand weighed toward end of fiscal year, with lead customer transitioning to 200-millimeter wafers. In hard disk drives, installing additional FOX-CP systems with plans for more purchases later.
• Packaged-part burn-in: Secured key new device wins for Sonoma system supporting high-temperature operating life qualifications for AI devices. Received over $5.5 million in orders for Sonoma systems in fiscal third quarter to date. Lead customer for AI processors is ramping and forecasting substantial growth, with a large forecast for AI ASIC production capacity. Completed development of next-generation fully automated higher-power Sonoma system.

Guidance

• Reinstated financial guidance for fiscal '26. Second half of fiscal '26 (Nov 29, 2025 - May 29, 2026) expected revenue between $25 million and $30 million. Bookings in second half of fiscal '26 expected to be between $60 million and $80 million, setting up strong fiscal '27 starting May 30, 2026.
• For second half of fiscal '26, total revenue expected between $25M - $30M, and non-GAAP net loss per diluted share between negative $0.09 and negative $0.05 for the 6-month period.

Risks

• Uncertainties in customer adoption of wafer-level burn-in solutions, including delays in benchmark processes for certain customers.
• Challenges in scaling production and meeting aggressive customer forecasts for high-demand segments like AI processors.
• Market competition and technological advancements that could impact the relevance of existing products and the company's ability to stay ahead.

Question and Answer

Q: What wasn't clear to me exactly is on the booking strength -- potential booking strength of $60 million to $80 million in the second half of this fiscal year. Is that almost entirely on the AI accelerator processor line?

A: There's some silicon carbide, not much, like not very much at all. There is some silicon photonics for sure. But the bulk of it is across wafer-level and packaged-part burn-in for AI processors, yes.

Q: Given that such a material bookings from the AI processor market, can you give us any indication or idea? I know we've talked about the opportunity in that marketplace being bigger than silicon carbide. But let's narrow it down to kind of a multiyear time frame kind of including '27 and '28. Do you see that business after initial orders expanding meaningfully from there?

A: We do. We do. And we've been taking a pretty conservative stance on how large, particularly the AI and the wafer level side of it is. Candidly, we're still trying to get our arms around how big it is...

Q: On the wafer level, I think your prior comments around the timing of the benchmark, it seems like that's taken a little bit longer. And I'm just wondering, is that a function of -- is it because it's new and what you're seeing is from the customer is that they're changing parameters that's extending that out?

A: No, I got it. What I do in all of these things is try to describe exactly what we feel, what we know, what we knew at the time. This -- one of the things that's very interesting and fun about this particular customer who is a very notable customer...

Q: First one for me, just around the bookings guide. I know you previously shared that majority of around AI. But just given the distinction between the low end and the high end, if we just take the midpoint of around $70 million, I mean, what -- to get to that $80 million, is that all basically around AI? Or does that suggest any improvement around silicon carbide or GaN?

A: It's the least in that number is silicon carbide, okay? And then GaN is pretty close. Hard disk drive is a little bigger. Then silicon photonics is a chunk...

Q: We try to line up your ramp or at least your demand for the systems that you're working on developing for these customers on the AI processors with what's publicly disclosed in terms of the product launch. Is there a case where they may start up on packaged part wherever they have the capacity to do that. And then when they feel comfortable, maybe if it's after the products launched, would they cut over the wafer level burn-in because it's so much more efficient and saves them money? Would they do that? Or would they just do it initially on a brand-new product launch at the beginning? That's kind of -- do you have a sense of that?

A: Okay. So I wouldn't -- there's 2 things in there. What I definitely see happening is we know for a fact a customer was doing system level or rack test...

Q: I recall you originally said the driver, their motivation was as the 3D NANDs got higher levels of -- they're even talking about getting the 400 level. Layers, that required more power and exceed the power in their existing systems so that they need your high power. So here we are 1.5 years later. And so how are they getting by to this point? And don't they need your high-power capability?

A: They're doing -- they're having to -- they can't test a whole wafer in one touch down as an example. But that -- what I described there, which people -- if you follow along with that, that was actually referred to as hybrid bonded flash same letters by the way, right? Hybrid bonded flash was a novel idea that the base substrate layer was logic done on the logic process and then you build up just the stacked memory, and you do that in a memory process and then you bond them together...